Reduced models for the behavior of VLSI circuits
Abstract
Several aspects of the modeling of the behavior of integrated circuits are addressed for verification purposes. The modeling of interconnect resistance in integrated circuits is described. The distribution of the interconnect capacitances over the resistance network is important to characterize the transmission behavior of the interconnections. The modeling of three dimensional capacitive effects between the interconnections of integrated circuits is discussed. The three dimensional capacitive effects become more prominent as the horizontal dimensions of the circuit are scaled down, while the vertical dimensions are unchanged. In order to compute reliable capacitance values for the most critical parts of the circuit, an accurate yet numerical technique that directly computes the capacitance values from the layout description of the circuit is described. A simulation model for quickly simulating the logic and timing behavior of large digital MOS circuits is described. Although the simulation model presented is not as accurate as the simulation model employed by a circuit simulator like Spice, it provides useful information about resistance division effects, charge sharing effects, delay times, spikes, and races occurring in the circuit, and it can be used, unlike Spice, to simulate on a workstation, in a reasonable amount of time, circuits containing over 100,000 transistors.
 Publication:

Ph.D. Thesis
 Pub Date:
 1991
 Bibcode:
 1991PhDT........27V
 Keywords:

 Electric Connectors;
 Electrical Resistance;
 Systems Simulation;
 Three Dimensional Models;
 Very Large Scale Integration;
 Capacitance;
 Metal Oxide Semiconductors;
 Proving;
 Electronics and Electrical Engineering