V.DMOS transistor modeling for simulation of power electronic circuits

A nonlinear, short channel model of a power V.DMOS transistor, the elements of which depend only on physical and technological data, is presented. By an analysis of the active regions of the V.DMOS structure, in order to study switching modes, this model is simplified to a topology compatible with the SPICE circuit simulator. Parameter extraction methods and validation programs are described. A software library of the SPICE models is created by testing the transistors (N and P channels) covering the available current handling capability 2A to 50A and blocking range 50V to 1000V. A V.DMOS unified model is presented. It requires establishment of two parameters: drain source breakdown voltage, and silicon chip area. An established program linked in Hypercard with SPICE, gives an exact model for characterizing transistors as well as a model for new devices. This modeling takes into account the crystal temperature and several validation tests. Adaptation of the model for irradiation applications is pointed out by comparison between measured and computed characteristics. Use of this model to analyze bridge leg circuit properties and comparison between simulated results and measured data, confirms its application in power electronic circuits. Some problems associated with parasitic elements in these circuits are described.