Phosphorus implantation into polycrystalline silicon (poly-Si) has been used to dope the gate electrodes in poly-Si and polycide structures. Effects of phosphorus implantation conditions and post-implantation annealing on the time zero dielectric breakdown (TZDB) characteristics of gate oxides of thicknesses 10, 20 and 30 nm were investigated. Higher implantation energy and higher post-implantation annealing temperature result in worse TZDB properties of the gate oxides. Especially, the TZDB characteristics of 10-nm-thick oxides after annealing show a much more significant dependence on the phosphorus implantation energy and post-implantation annealing temperature than those of thicker oxides. Therefore, phosphorus diffusion into the SiO 2/Si interface is the main cause of deterioration of the gate dielectrics. The thicker oxide has a higher endurance to the phosphorus diffusion and consequently achieves a better dielectric property for the higher energy implantation and higher temperature annealing conditions.