Dynamic complementary metal oxide semiconductor (CMOS) circuits have been a privileged target for the optimization of characteristics such as speed, area, and power dissipation. Research was conducted to reduce the delay of classes of CMOS logic circuits by inserting a parallel regenerator at specific nodes. The new design method presented is shown to reduce the delay by as much as 80% and the delay-area product by up to 35%. Results of different circuit simulations using the HSPICE simulator, assuming Northern Telecom CMOS3DLM technology parameters are summarized.
Electrical and Computer Engineering, Volumes 1 and 2 4 p (SEE N93-30215 11-31)
- Pub Date:
- Logic Circuits;
- Computerized Simulation;
- Electronics and Electrical Engineering