Gallium Arsenide Charge-Coupled Device Circuits for High-Speed Signal Processing

Analog, charge-domain arithmetic circuits, with relevance to a wide variety of image and signal processing applications, are investigated. In addition, novel GaAs charge-coupled device architectures are explored. These new structures improve MESFET compatibility and extend the operating bandwidth of GaAs CCD's. Two charge-domain arithmetic circuits are described: (1) a charge packet replicator/subtractor and (2) a charge packet multiplication circuit. Each of these utilizes the very low parasitic capacitance of the GaAs semi-insulating substrate. Analysis of circuit performance versus operating speed is discussed, with design criteria and modelling results presented. The charge packet replicator/subtractor experimentally demonstrates linear, near unity gain over the operating range of 1 MHz to 1 GHz. Subtraction or replication take place in one clock cycle. The charge packet multiplier is composed of two replicator/subtractor circuits and a small shift register. Using data from experimental characterization of each of these components, the charge packet multiplier is predicted to exhibit 8 bit equivalent accuracy, while operating at 1 GHz clock rate. Theoretically, one charge packet multiplier is capable of 250 million 8 bit multiplications per second. A recessed-gap GaAs CCD architecture is shown to improve MESFET compatibility by eliminating the parasitic potential wells generally associated with open-gap CCD's. Previous work in this area has centered on the use of submicron interelectrode gaps, with the undesirable side-effects of increased parasitic gate-to-gate capacitance and lower gate-channel-gate breakdown voltage. The recessed-gap device structure permits use of an active layer compatible with high transconductance MESFET's and an interelectrode gap size of 1 micron or greater. A device architecture incorporating a thin AlGaAs cap layer is shown to extend the low frequency operating range of GaAs CCD's to 10 kHz. The AlGaAs cap layer increases the barrier height of the CCD gates, reducing the dark current contribution from gate leakage. The inclusion of the AlGaAs cap layer has minimal impact on device design and fabrication.