The single-event upset (SEU) characterization of GaAs enhancement/depletion (E/D) MESFET logic circuits was experimentally performed for five different logic families. The results indicate a large charge collection volume, independent of the logic family. These results can be attributed to a gate edge effect and an enhanced source-drain charge collection mechanism. The consequence of these effects is to increase the upset rate in space by more than two orders of magnitude. Soft-error rates were estimated for each logic family and spanned the range from 0.0023 to 0.00047 errors/bit-day.