A VLSI design for computing exponentiations in GF(2m) and its application to generate pseudorandom number sequences
Abstract
A VLSI design for computing exponentiation in finite fields is developed. An algorithm to generate a relatively long pseudorandom number sequence is presented. It is shown that the period of this sequence is significantly increased compared to that of the sequence generated by the most commonly used maximal length shift register scheme.
- Publication:
-
IEEE Transactions on Computers
- Pub Date:
- February 1990
- Bibcode:
- 1990ITCmp..39..258W
- Keywords:
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- Error Correcting Codes;
- Exponents;
- Pipelining (Computers);
- Random Numbers;
- Very Large Scale Integration;
- Algorithms;
- Decoding;
- Flow Charts;
- Multiplication;
- Communications and Radar