A strategy of built-in test implementation
Abstract
A methodology aimed at easing the DFT (design for testability) task of highly complex logic composed of many application-specific integrated circuits (ASICs) is described which has been in use for several years at ESD. This methodology, called the hierarchical built-in self-test, provides to the designer a homogeneous and straightforward approach to solving the various test problems involved, from component to system level, in manufacturing, maintenance, or in-use stages. This methodology is characterized by the fact that the designer can benefit at a specific level of design (board, hybrid, ASIC) from the work previously done at the next lower abstract level. A signal-processing example is presented to illustrate the approach.
- Publication:
-
Radar 89, Volume 2
- Pub Date:
- 1989
- Bibcode:
- 1989rada....2..398R
- Keywords:
-
- Application Specific Integrated Circuits;
- Experiment Design;
- Self Tests;
- Design Analysis;
- Hierarchies;
- Logic Design;
- Systems Engineering;
- Communications and Radar