Investigation of the feasibility of a signal processor for a spaceborne SAR

The paper examines the concept of raw data processing with an onboard computer to reduce the down link data for a spaceborne SAR. This computer must provide several billion operations per second on a memory of several hundred Mbits per second. It requires the development of an ASIC processor in CMOS technology, implementing a stage of a base 2 FFT with a rate of 20 megasamples per second. The feasibility of such a processor has been demonstrated for a remote sensing system planned for the year 2000. A first design is presented here in terms of mass, volume, and power consumption, leading to an acceptable solution for the satellite payload.