GaAs gate dynamic memory technology

The expected performance characteristics of GaAs dynamic memories are compared with the capabilities of existing technologies to establish a speed capacity window for possible applications. The design of GaAs dynamic memories using FET direct access of PN-junction based storage capacitors is developed. The leakage mechanisms in PN-junction capacitors are considered theoretically, and experimental performance of mesa-isolated capacitors in GaAs and AlGaAs is reported. Optimization of storage time performance and charge capacity by selection of materials and dopings is discussed, and the limitations of optimized capacitors with respect to temperature and scaling are examined experimentally, MBE-grown mesa-isolated PN-junction capacitors are demonstrated to have both sufficient storage time and sufficient capacity for high density GaAs DRAMs operating above 100 C. Design of access transistors for optimal subthreshold performance is discussed. A 2-D harmonic solution for the potential in subthreshold FETs is presented. The harmonic solution is used to calculate the relationships between physical FET design parameters and subthreshold performance. Trade-offs between design for best subthreshold characteristics versus manufacturability and circuit requirements are considered. The design of complete DRAM cells combining a capacitor and an access transistor is developed. Required operating voltages for read, write, and storage sequences are established.