The effect of layout, substrate/well biases, and triggering source location on latchup triggering currents in bulk CMOS circuits
Based on the experimental measurement of latchup triggering currents, the effects of contact placements in wells, triggering source location and substrate/well bias on latchup immunity of p- n- p- n structures in bulk CMOS circuits are extensively investigated and characterized. From the measured triggering currents, latchup behavior due to external triggering sources can be more definitely understood. It is found that triggering current depends not only on the layout connections for a p- n- p- n structure but also, in most cases, strongly on the location of triggering sources as well as the substrate or well bias. An analytic model is derived to describe the dependence of the triggering current on the substrate or well bias. The substrate (well) triggering current is found to be linearly (linearly) dependent on the substrate (well) bias and to increase with increase of the well (substrate) bias.