An NTSC-CIF mutual conversion processor is developed that consists of just four VLSI chips, and external four frame memories and five field memories. The new processor can reversibly convert NTSC signals into any one of the four CIF formats. The processor replaces conventional systems consisting of several hundred chips with commensurately lower cost and power consumption. Many circuit devices are developed for the processor. A new PLL circuit, similar to a "tanlock loop" for color demodulation, detects phase error between input and local color sub-carrier by looking up a ROM table. By limiting the detectable phase error range to +/- 45 degrees, the ROM capacity is drastically reduced to 1/146 of that needed for +/- 90 degrees. In order to avoid picture degradation, parallel different band-width filters are adopted. Coefficient sets of horizontal and vertical filters are shared by the four formats. A pre-filter smoothes motion and reduces noise. It utilizes the double buffer frame memories to minimize the required external memory capacity. The VLSI chips are constructed with the advanced Bi-CMOS technology. A 0.8 micron design rule is used and the die size is 144 mm2. A 208-pin PGA package format is used.