Automated Gate Matrix Layout of CMOS Circuits.

In this dissertation, we consider the problem of obtaining a layout of a CMOS circuit based on the gate matrix style. The problem is formulated as one of finding two functions, a gate sequencing function, f, which maps the transistor gates onto the columns of the gate matrix, and a net assignment function, h, which maps the nets that connect the gates and transistors, to the rows. Algorithms are developed to find f and h such that the layout area is minimized and that certain practical constraints such as short vertical connections are realizable. In addition, for the first time, oversized transistors, series-connected transistors, and pre-fixed input/output terminals are taken into consideration in the algorithms. Secondly, we consider the problem of partitioning a large circuit into sub-circuits, each of which is realized in a gate matrix such that the overall area is minimized with acceptable aspect ratio. Experimental results show that the total area of the partitioned matrices is reduced from an unpartitioned matrix by 11% to 41%. The algorithms to find functions f and h have been integrated into a layout program, GM, which takes a circuit description as the input and generates a gate matrix layout in physical patterns. Power connections are also implemented in GM. The algorithms to obtain partitioned gate matrices are integrated into a partitioning program, GMP, which takes a circuit description and produces a number of partitioned matrices. The output from GMP is then processed in GM to generate layout patterns of the partitioned matrices. The programs have been applied to examples of circuits containing of up to 462 transistors and the layout of the largest circuit is obtained in about 8 minutes.