Built in test of folded PLAs

A built-in self test of topologically optimized Programmable Logic Arrays (PLAs) is examined. A review of PLA optimization techniques is presented. From these techniques, the built-in self test scheme is selected. This scheme is shown to be an improvement over other existing schemes. Its convenience in handling topologically optimized PLAS is shown. The application of the scheme to different optimization techniques is discussed in detail. The compatibility of other built-in self tests for PLA methods with topological optimization is discussed.