Noisemargin limitations on galliumarsenide VLSI
Abstract
Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.
 Publication:

IEEE Journal of SolidState Circuits
 Pub Date:
 August 1988
 DOI:
 10.1109/4.339
 Bibcode:
 1988IJSSC..23..893L
 Keywords:

 Field Effect Transistors;
 Gallium Arsenides;
 Logic Circuits;
 Noise Spectra;
 Schottky Diodes;
 Very Large Scale Integration;
 Heterojunctions;
 Ion Implantation;
 NType Semiconductors;
 Random Access Memory;
 Electronics and Electrical Engineering