SOI technology offers improved circuit performance due to the reduced junction capacitance, latch-up free dielectric isolation, higher packing density and higher radiation tolerance. Some of the SOI approaches can offer an IC fabrication which is compatible with, but simpler than, the bulk CMOS process, especially with scaled geometries; and they can make the Bi-CMOS process integration easier, due to the simplicity in the device isolation process. Some approaches can also be applied to 3-D IC's through multi-layered SOI structures. The realization of these advantages, however, hinges on obtaining a device quality single crystal silicon on top of an insulator. Status, advantage, and disadvantage of various SOI approaches are presented in this paper with particular emphasis placed on the SIMOX approach which in the past couple of years has emerged as the leading SOI technology an offers and opportunity to be a viable cost effective alternative to the sub-half micrometer bulk CMOS scaling.
Deposition and Growth: Limits for Microelectronics
- Pub Date:
- September 1988
- Lithography masks and pattern transfer;
- Methods of deposition of films and coatings;
- film growth and epitaxy;
- Metal-insulator-semiconductor structures