Production, Characterization, and Uses of Thin Semiconductor Membranes.

One of the factors limiting the speed of present devices is parasitic impedances. Devices made on single crystal semiconductor membranes less than one micron thick offer unique possibilities for reducing these parasitic impedances by enabling new device designs that utilize both surfaces of the membrane. This thesis addresses the problems associated with making such thin membranes, and making devices on them. A new method for producing submicron thick single crystal semiconductor membranes is presented. It relies on the controlled introduction of lattice damage using ion implantation to reduce the hole concentration in a submicron thick layer on one side of a semiconductor wafer. The unimplanted part of the wafer is then anodically etched, leaving the implanted layer behind as the membrane. The ion implantation damage is then removed by annealing. The suitability for device applications of the membranes made using this new technique was determined by characterizing their crystalline and electrical quality. The membranes were examined in a transmission electron microscope both before and after annealing. It was found that the damage present after implantation could be removed by a suitable annealing treatment. Using the technique of convergent beam electron diffraction, it was found that the thicknesses of the silicon membranes were very nearly equal to the projected ranges of the ions implanted, whereas in GaAs, the membranes were about twice as thick as the projected ranges, in agreement with published observations by other workers. To characterize the membranes electrically, a Schottky barrier diode was made on a 150 nm thick silicon membrane. The Schottky barrier contact was made on one surface of the membrane, while the ohmic contact was made on the opposite side of the membrane. The ideality factor determined from current voltage measurements agreed to within the experimental error with expectations. The impurity concentration profile determined from capacity voltage measurements agreed with predictions based on the processing parameters. The cutoff frequency of this diode was estimated to be about 2 THz, which is one to two orders of magnitude above the highest cutoff frequency of planar silicon Schottky diodes currently being made on thick wafers.