Timing and area optimization of CMOS combinationallogic circuits accounting for totaldose radiation effects
Abstract
An algorithm for optimizing CMOS VLSI combinational logic circuits for operation in totaldose environments is presented. The widthtolength ratios of the MOS transistors that allow the circuit to meet specified timing requirements while minimizing circuit area are determined. The logic circuit is modeled by an equivalent resistorcapacitor (RC) network, where the resistors and capacitors are functions of transistor widthtolength ratios. The totaldose radiation dependence is modeled as a variation in the resistors. The algorithm has been implemented and tested on example circuits, and the results have been verified using SPICE.
 Publication:

IEEE Transactions on Nuclear Science
 Pub Date:
 December 1987
 DOI:
 10.1109/TNS.1987.4337485
 Bibcode:
 1987ITNS...34.1386G
 Keywords:

 Cmos;
 Logic Circuits;
 Optimization;
 Radiation Dosage;
 Radiation Effects;
 Equivalent Circuits;
 Metal Oxide Semiconductors;
 Rc Circuits;
 Transistor Circuits;
 Very Large Scale Integration;
 Electronics and Electrical Engineering