Timing and area optimization of CMOS combinational-logic circuits accounting for total-dose radiation effects

An algorithm for optimizing CMOS VLSI combinational logic circuits for operation in total-dose environments is presented. The width-to-length ratios of the MOS transistors that allow the circuit to meet specified timing requirements while minimizing circuit area are determined. The logic circuit is modeled by an equivalent resistor-capacitor (RC) network, where the resistors and capacitors are functions of transistor width-to-length ratios. The total-dose radiation dependence is modeled as a variation in the resistors. The algorithm has been implemented and tested on example circuits, and the results have been verified using SPICE.