Dynamic cross-coupled bit-line content addressable memory cell for high-density arrays

This paper describes the design of a novel dynamic content addressable memory (CAM) cell suitable for high-density arrays. The proposed cell is capable of storing three internal states: one, zero, and 'don't care' (MASK). The cell consists of five NMOS transistors of which four are used to store and access data and one is used as a diode to isolate current paths. Charge is stored on the gate of a transistor which results in nondestructive current-driven READ and MATCH operations and increases the charge storage time leading to higher reliability and improved immunization to alpha particles. Using 2-micron design rules, buried contacts, single-level metal, and low-resistance polycide lines results in a CAM cell area of 25 x 22 sq microns which is comparable to 64-kbit static random access memory cell areas. The CAM cell was successfully fabricated using a 4-micron NMOS process and its operation was verified with a 2 x 3-bit array.