This document reports on the research activities of the UW/NW VLSI Consortium. During this period, the Consortium staff refined a number of the design generators reported on in the last Technical Report. Two substantial design efforts, a 32 bit microprocessor and a digital filter, utilized several of the generators. Ongoing work focuses on development of interfaces to verification tools such as the DRC and switch level simulators, as well as a functional simulator currently under development. Such interfaces allow the verification tools to make use of the correctness of instances created by generators. A preliminary model for generator construction has been proposed. The intent of the model is to provide a concise specification of the circuit from which a number of output descriptions such as the layout, schematic and transistor netlist may be derived. The model has been applied to both a decoder and a multiplier generator. Work is progressing on a simulation system intended to provide a broad range of capability - from high level behavioral modeling to low level transistor modeling. The system is intended to be used to simulate assemblies of circuits produced by the design generators as well as hand crafted circuits.
Semiannual Technical Report
- Pub Date:
- March 1986
- Digital Filters;
- Very Large Scale Integration;
- Design Analysis;
- Electronics and Electrical Engineering