A technique for a hierarchical design of delay-insensitive circuits is presented. The technique is developed by means of the trace-theory formalism. The design consists of the formulation of a specification and its decomposition into basic elements. Parallelism is allowed in a specification. The notion of delay-insensitive circuit is formalized. Three examples illustrate the technique.
NASA STI/Recon Technical Report N
- Pub Date:
- June 1986
- Very Large Scale Integration;
- Functional Design Specifications;
- Parallel Processing (Computers);
- Electronics and Electrical Engineering