Structured Built-In Test for Lsi/vlsi Chips Based on Random Patterns.

The vast increase in VLSI circuit density has increased the problem of chip and system testing. In recent years, numerous techniques have been proposed in the Design for Testability literature to ease the LSI/VLSI chip testing problem, with special emphasis on Built-In Self Test (BIST) techniques. In this work, a very cost-effective random self-test structure is proposed for LSI/VLSI chips. The idea behind the self-test structure proposed here is to minimize built-in test logic by eliminating the linear feedback shift register nomally required for test generation. One major problem in self-testing with random tests is verification of test quality, i.e. determining the fault coverage as function of the number of random patterns used in a test. In this work, an analytical method to determine random test length required for a given degree of test quality from functional description of the device is presented. A relatively simple rule for designing easily testable circuit modules based on a lower bound fault detection probability analysis is also described. The proposed test structure is especially useful for systems containing a large number of flip-flops. The concepts of scan path and signature analysis are integrated into the new test structure.