A communication bandwidth model for shuffleexchange and augmented shuffleexchange interprocessor communication networks
Abstract
A failure dependent bandwidth model for shuffle exchange (S/E) and augmented shuffle exchange (S/E+) interconnection networks is presented. The models are based on probabilities of either data or address mode failures for the individual binary switches which comprise the SE or SE+ network. The model gives the expected bandwidth as a function of the probability of failures in these switches. The model, which is consistent with those previously published when the probability of failure is zero, is first developed for the S/E network. This model is extended to the S/E+ network by developing a special model for the input stage of the S/E+ network and then proving that, to within a close approximation, the conditions necessary for the S/E model hold at the outputs of first stage of the S/E+. The model is verified using a computer simulation. An example is presented which demonstrates use of the model to predict the effects of several fault tolerance schemes on the bandwidth of these networks. The model demonstrates that, when used as a reliability enhancement, the extra stage of the S/E+ causes a reduction in bandwidth as compared to an S/E network.
 Publication:

Ph.D. Thesis
 Pub Date:
 1986
 Bibcode:
 1986PhDT........21B
 Keywords:

 Bandwidth;
 Communication Networks;
 Computer Networks;
 Computer Systems Simulation;
 Interprocessor Communication;
 Parallel Processing (Computers);
 Reliability Analysis;
 Computerized Simulation;
 Fault Tolerance;
 Memory (Computers);
 Models;
 Switching Circuits;
 System Failures;
 Communications and Radar