A high-performance N-MOS adder designed for optimized cryogenic operation
Abstract
An N-MOS process for low-temperature operation has been developed using argon-implanted polysilicon resistors as loads in invertors. The process has been implemented in a high-speed 3-bit adder designed with 3- and 2.4-micron rules and running at 320 and 405 MHz, respectively for power consumptions of 32 and 28 mW. Test results are presented and compared with results from the same circuit realized with other technologies, such as submicrometer N-MOS, LPBFL GaAs, STL, and classical N-MOS.
- Publication:
-
IEEE Journal of Solid-State Circuits
- Pub Date:
- June 1986
- DOI:
- 10.1109/JSSC.1986.1052542
- Bibcode:
- 1986IJSSC..21..404G
- Keywords:
-
- Adding Circuits;
- Low Temperature;
- Metal Oxide Semiconductors;
- Vhsic (Circuits);
- Electronic Equipment Tests;
- Implantation;
- Logic Design;
- Microelectronics;
- Network Synthesis;
- Optimization;
- Resistors;
- Electronics and Electrical Engineering