Design of a standard floating-point chip
Abstract
Some aspects of the methodology, floor planning, and circuit design used in developing a VLSI floating-point chip for a 32-bit microprocessor are examined. The chip is about 1 sq cm in area and is fabricated in 1.75-micron CMOS; it dissipates about 900 mW of power when running at 14 MHz. Several design and layout techniques utilized to achieve high performance are discussed, including the design of a unique input multiplexer.
- Publication:
-
IEEE Journal of Solid-State Circuits
- Pub Date:
- June 1986
- DOI:
- Bibcode:
- 1986IJSSC..21..396T
- Keywords:
-
- Arithmetic And Logic Units;
- Chips (Electronics);
- Floating Point Arithmetic;
- Microprocessors;
- Network Synthesis;
- Very Large Scale Integration;
- Cmos;
- Logic Design;
- Microelectronics;
- Multiplexing;
- Transistor Circuits;
- Electronics and Electrical Engineering