Power distribution techniques for VLSI circuits

The on-chip power distribution problem for highly scaled technologies is investigated. Metal migration and line resistance problems as well as to optimize multilayer metal technology for low resistance, low current density, and maximum wirability are also investiated. Fundamental lower limits and the limiting factors of the power-line current density and the voltage drop are studied. Trade-offs between interconnect wirability and power distribution space are examined. Power routing schemes, as well as the optical number of metal layers and the optimal thickness of each layer, are examined. The results indicate that orders of magnitude improvements in current density and resistive voltage drop can be achieved using very few layers of thick metal whose thicknesses increase rapidly in ascending layers. Also, using the upper layers for power distribution and lower layers for signal routing results in the most wire length available for signal routing. For the current MOS VLSI technology, one or two additional thick layer(s) should solve most of the power distribution problems.