VLSI structures for Viterbi receivers. I - General theory and applications. II - Encoded MSK modulation

The implementation of certain digital communication receiver types based on the Viterbi algorithm is presently based on a taxonomy of VLSI grid model layouts in which emphasis is given to networks of many simple processors connected to perform the Viterbi algorithm in a highly parallel fashion. Attention is given to the shuffle exchange and the cube-connected cycle interconnection patterns. A second part of this work elaborates ways in which the concepts presented can be applied to the construction of encoded MSK Viterbi receivers; lower bounds are established on the product of chip area and baud rate exp -2, and on the energy consumption that any VLSI implementation of the Viterbi algorithm must obey irrespective of the architecture employed or the application intended.