Soft-error filtering - A solution to the reliability problem of future VLSI digital circuits

A technique, referred to as Soft-Error Filtering (SEF), is proposed for reducing the error rate due to transients induced in scale-down VLSI digital circuits. The technique involves filtering the input to every latch in the VLSI circuit, thereby preventing the transients generated by alpha particle hits in the combinatorial section from being latched in the corresponding registers. A double-filter implementation of the filtering latch is described, and it is shown that this design is simple, efficient, and tolerant to process variations. The advantages of the SEF approach over other methods for dealing with soft errors are discussed.