Numerical analysis of heavy ion particle-induced CMOS latch-up
Abstract
Assuming a two-dimensional spreading of a sheet of a charge in a plane, a two-dimensional transient numerical simulator is used to analyze heavy ion particle-induced CMOS latch-up. The charge funneling effect during the carrier collection process is found to lower the parasitic bipolar emitter-base potential barrier, which is the main factor initiating latch-up. Latch-up susceptibility is examined as a parameter of the heavy ion particle incident condition, with track lengths taken as 8 microns. The incident conditions demonstrating long path length in the N-well/P-sub junction depletion layer were shown to be the most sensitive to latch-up, and the use of an n+ guard band was found to be more effective for latch-up immunity. The study has LSI space applications.
- Publication:
-
IEEE Electron Device Letters
- Pub Date:
- May 1986
- DOI:
- 10.1109/EDL.1986.26371
- Bibcode:
- 1986IEDL....7..273A
- Keywords:
-
- Carrier Transport (Solid State);
- Cmos;
- Heavy Ions;
- Latch-Up;
- Radiation Damage;
- Transient Response;
- Bipolar Transistors;
- Computerized Simulation;
- Electric Potential;
- Emitters;
- P-N-P-N Junctions;
- Electronics and Electrical Engineering