A simple method to improve the noise margin of III-V DCFL digital circuit coupling diode FET logic
Abstract
This paper proposes a novel method to increase the noise margins achievable with III-V Direct Coupled FET Logic digital circuits. The idea is to increase the forward-biased potential obtainable on the gate of the enhancement device before substantial conduction occurs. The method proposed here is to simply add a diode in series with the gate. Circuit simulations (MESFET and HFET) and device theory are given to support the feasibility of the Coupling Diode FET Logic (CDFL). A novel device structure, compatible with the semiconductor-gate HFET, also will be given.
- Publication:
-
IEEE Electron Device Letters
- Pub Date:
- March 1986
- Bibcode:
- 1986IEDL....7..145Y
- Keywords:
-
- Digital Electronics;
- Field Effect Transistors;
- Gallium Arsenides;
- Logic Circuits;
- Noise Reduction;
- Semiconductor Diodes;
- Transistor Logic;
- Electrical Properties;
- Gates (Circuits);
- Heterojunction Devices;
- Vhsic (Circuits);
- Electronics and Electrical Engineering