High-speed and high-coding-gain Viterbi decoder with low power consumption employing SST (scarce state transition) scheme
Abstract
A high-speed and high-coding-gain Viterbi decoder LSI with low power consumption is developed using CMOS master-slice LSI. By employment of the SST (scarce state transition) scheme, this LSI achieves a good Pe performance (4.2 dB net coding gain at Pe = 1 x 10 to the -6th), drastic reduction of power consumption and number of gates with low development costs.
- Publication:
-
Electronics Letters
- Pub Date:
- April 1986
- DOI:
- 10.1049/el:19860334
- Bibcode:
- 1986ElL....22..491K
- Keywords:
-
- Binary Codes;
- Cmos;
- Decoders;
- Digital Systems;
- Error Correcting Codes;
- Large Scale Integration;
- Viterbi Decoders;
- Convolution Integrals;
- High Speed;
- Network Synthesis;
- Performance Tests;
- Communications and Radar