Modèle de boucles à verrouillage de phase numériques fonctionnant à faible rapport signal sur bruit

A general model for digital phase-locked loops (PLL) with low SNR (under 10 dB) is presented for use in designing new circuits and predicting their performance. The PLL consists of a phase error detector, a filter for the flagged error signal, and an oscillator controlled by signals from the error detection filter. The model is developed for loops using either an integrator or a sampler with a quantifier as the phase detector. Consideration is given to the performance of the loop in the presence and the absence of noise. Applications of the model for a first-order loop and a loop with a sequential filter are described.