MOS integrated circuit fault modeling
Abstract
Three digital simulation techniques for MOS integrated circuit faults were examined. These techniques embody a hierarchy of complexity bracketing the range of simulation levels. The digital approaches are: transistor-level, connector-switch-attenuator level, and gate level. The advantages and disadvantages are discussed. Failure characteristics are also described.
- Publication:
-
In its Product Assurance Technology for Custom LSI/VLSI Electronics 15 p (SEE N86-29255 20-38
- Pub Date:
- June 1985
- Bibcode:
- 1985patc.nasa.....S
- Keywords:
-
- Computerized Simulation;
- Electrical Faults;
- Fault Tolerance;
- Integrated Circuits;
- Metal Oxide Semiconductors;
- Models;
- Failure Analysis;
- Failure Modes;
- Photolithography;
- Signal Fading;
- Transistors;
- Wear;
- Electronics and Electrical Engineering