Direct moat self-aligned field oxide technique

A process is used to produce high density radiation hardened Complementary Metal Oxide Semiconductor (CMOS) circuits. The steps are as follows: (1) growing a field oxide layer including any specialized hardening techniques thereto on a silicon wafer; (2) depositing a material which will serve as an implant mask such as aluminum; (3) etching this layer to leave shapes where the thin oxide gate regions are to be; (4) depositing a spacer material such as sputtered nitride onto the shapes; (5) etching the spacer material; (6) depositing a field implant mask; (7) etching the implant mask; (8) implanting the field regions; (9) stripping the implant mask; (10) stripping the spacer material is used; (11) depositing a secondary masking layer such as Ti-W or W; (12) bias sputtering away secondary masking material at edges of aluminum shapes; (13) removing aluminum shapes using secondary material as a mask; (14) etching oxide under aluminum shapes to reach the silicon wafer; (15) stripping secondary masking layer; (16) growing gate oxide; (17) removing field oxide layer to expose source and drain regions in the wafer; and (18) placing electrodes into the drain, source and gate regions.