Method of characterizing critical timing paths and analyzing timing related failure modes in very large scale integrated circuits

A method characterizes critical timing paths and analyzing timing related failure modes in high clock rate photocurrent at the drain of a single transistor in a very large scale integrated circuit. The laser testing apparatus utilized with the method of this invention incorporates therein a laser having its output beam focused onto the drain junction of the transistor under test. The locallized injection of electromagnetic radiation produces a photocurrent at the drain junction at specific times during the testing procedure which increases the logic level transition times associated with that particular node. This causes an increase in the minimum operating power supply and/or a decrease in the maximum operating frequency at which the microcircuit will properly function. Consideration of these parameters and the level of photocurrent provide a measurement related to the worst case timing margin which occurs during functional test of the integrated microcircuit.