Processing requirements for radar digital beamforming

An overview is given of the signal processing capabilities of radar DBF systems. Also, a description is given of advances required in existing hardware for implementing real-time signal processing on radar DBF systems. These include antenna elements, monolithic microwave integrated circuits and VLSI. A discussion is given of the advantages of novel architectures, such as systolic arrays or hypercubes using up to 10,000 processing elements. It is shown that the processing for a DBF system follows naturally from a set of basic matrix operations, running from matrix-vector multiplications to singular value decomposition of matrices and that these functions are best implemented using systolic-array type architectures. Finally, results will be presented from an existing near real-time DBF system which is capable of carrying out a 16-point complex FFT in 250 nanoseconds and produces 64 independent radar-beams in 4 microseconds.