EMI noise susceptibility of ESD protect buffers in selected MOS devices

This paper presents the results of an effort to determine the changes in the EMI noise susceptibility of selected MOS integrated circuits due to the presence of Electrostatic Discharge protection networks integral to the host chip. The approach taken combines laboratory measurements with computer aided circuit simulations. EMI noise stimuli are laboratory generated and applied as Continuous Wave (CW), AM CW, and impulse waveforms, in the frequency range from 5 to 300 MHz. These extraneous noise signals (EMI) are capacitively coupled into MSI and LSI CMOS and NMOS devices under test, while appropriate functional signals are applied. Our results indicated that select input protect circuitry diminishes the effect of pulsed EMI with a fast rise time and an exponentially decaying fall time. However, the protect circuitry appears in some cases to enhance the effect of 100 percent square wave modulated EMI from 20 MHz to 200 MHz.