Compaction with automatic jog introduction

A novel polynomial-time algorithm for compacting a VLSI layout is presented. Compared to previous algorithms, the algorithm promises to produce higher quality output while reducing the need for designer intervention. The performance gain is realized by converting wires into constraints on the positions of the active devices. These constraints can be solved by graph-theoretic techniques to yield optimal positions for chip components. A single-layer router is then used to restore the wires to the layout, using as many as jogs as necessary. An automated compaction procedure is an effective tool for cutting production costs of a VLSI circuit at low cost to the designer, because the yield of fabricated chips is strongly dependent on the total circuit area. Sect 1 is an introduction. Sect 2 states the definitions and theoretical results that underlie the new compaction method. Sect 3 shows how the circuit layout is converted to a data structure appropriate for compaction, and Sect 4 details the body of the compaction algorithm. Sect 5 covers several improvements to the algorithm that should make it run considerably faster. Sect 6 comments on the algorithms of results, and a discussion of the practical value of the compaction algorithm.