Relative sizing of layout data to compensate for exposure errors on optical lithography systems
The processing of advance integrated circuits oftentimes employs the patterning of fine geometries of differing levels. This leads to a non-uniform thickness of photo-resist about the topologies and a built-in defocus for the optical projection lithography used to fabricate the integrated circuit itself. In the processing of these advanced integrated circuits according to the invention, the data is to be laid out with a predetermined reticule sizing based on the topological characteristics then of concern, so as to compensate for the defocussing previously associated with a single layer photo-resist process.
Patent Application Department of the Army
- Pub Date:
- November 1985
- Integrated Circuits;
- Patent Applications;
- Engineering (General)