A methodology for the design of testable custom large-scale integrated circuits

This report summarizes the main concepts in the design for testability of custom large-scale integrated circuits (CLSICs) and concepts involved in testing for physical faults in actual hardware. Important problems and issues which should be considered in designing a testable CLSIC, including test structures and design style, test strategies, test strategy measures, and testable design methodologies are introduced. A general methodology for designing a testable CLSIC is presented, which includes partitioning a chip into circuit structures, and imbedding each circuit structure into a suitable testable design structure. Measures are introduced so that different test methodologies can be quantitatively compared.