Development of a digital signal processor

A digital signal processor whose architecture was optimized for signal processing algorithms was developed. The processor has a multibus structure, distributed memories, and uses pipelined program execution. The basic arithmetic instruction is multiply and add, carried out within 2 instruction cycles of 100 msec each. Development tools such as cross-assembler, simulator (debugger), and in-circuit emulator are provided for the design of consumer applications. Due to its high computing speed and low power dissipation, the digital signal processor has a wide range of possible applications.