A network flow approach to the wafer scale integration of VLSI arrays
Abstract
An algorithm is described for reconfiguring a 2dimensional VLSI array on a silicon wafer that has some faulty cells. The functional cells of the array are interconnected in order to simulate a faultfree array of smaller size, where the interconnection wires are routed inside horizontal and vertical channels, according to the Manhattan model. The concept of simulation distance is introduced, and it is shown to be related to the length of the longest interconnection wire. The algorithm makes use of network flow techniques in order to find wiring with minimum simulation distance. This results in a practical heuristic for minimum simulation distance. This results in a practical heuristic for minimizing the maximum wire length. The complexity and performance of this algorithm are also discussed in the paper.
 Publication:

NASA STI/Recon Technical Report N
 Pub Date:
 June 1985
 Bibcode:
 1985STIN...8621759C
 Keywords:

 Algorithms;
 Arrays;
 Channels (Data Transmission);
 Computer Techniques;
 Electric Connectors;
 Fault Tolerance;
 Silicon;
 Simulation;
 Very Large Scale Integration;
 Wafers;
 Wire;
 Approach;
 Distance;
 Horizontal Orientation;
 Size (Dimensions);
 Electronics and Electrical Engineering