Area-time lower-bound techniques with application to sorting

The area-time complexity of VLSI (Very Large Scale Integration) computations is constrained by the flow and the storage of information in the two-dimensional chip. The information exchanged across the boundary of the cells of a square-tessellation of the layout is considered. When the information exchange is due to the functional dependence between variables respectively input and output on opposite sides of a cell boundary, lower bounds are obtained on the AT squared measure (which subsume bisection bounds as a special case). When information exchange is due to the storage saturation of the tessellation cells, a new type of lower bound is obtained on the AT measure. In the above arguments, information is essentially viewed as a fluid whose flow is uniquely constrained by the available bandwidth. However, in some computations, the flow is kept below capacity by the necessity to transform information before an output is produced. This mechanism is called computational friction and it is shown that it implies lower bounds on the AT/log A measure. Regimes corresponding to each of the three mechanisms described above can appear by varying the problem parameters.