Area estimation of VLSI integrated circuits

In this report, we present the problem of estimating the area of digital integrated circuits. This problem is important for reasons of chip yield, floor planning and design turnaround time. Area estimation is to be done at different levels of hierarchy. A model is presented for estimating the dimensions of the random logic blocks of a chip, given the description of these blocks as their constituent cells and their interconnections. We will pursue this research towards building a complete area estimation system which can handle different layout methodologies, can perform estimation at higher levels of design description (namely the Register-Transfer level), and be a useful aid to floorplanning and total layout as part of the ADAM system.