Design information for the 4/3 silicon-gate CMOS technology

Enclosed is a 3-Dimensional view of the 4/3 silicon gate layout, showing the different mask layers. The 4/3 design rules are explained in detail, both in written form and pictorially. An explanation of the VAX design rule check, plus charts showing alignment sequence, mask field tones and current biasing are included. Also included are various drawings explaining positive and negative resist, cross sectional view of a silicon gate layout and three examples of different 4/3 layouts (Flipflop, Memory, C(2)L) using the 4/3 design rules.