a New Implementation of the Pipeline Analog-To - Conversion Technique.

With the present trend towards digital LSI technology, the techniques of analog-to-digital conversion play a major role in the rapidly growing field of signal processing. For over two decades many approaches for A/D conversion have been explored. Among them two popular schemes; successive approximation and flash conversion techniques, are widely used at the present time. Successive approximation converters are structurally simple but are useful only for moderately low-speed applications. On the other hand, flash converters are extremely fast but require a substantial amount of circuitry. An alternative to the methods above, that has the advantages of those techniques without their drawbacks, is the pipelining approach to be described in this dissertation. A new implementation of this technique, which allows for realization of high speed A/D conversion without complex circuitry, is introduced. A discrete prototype of an 8 -bit pipeline converter, using commercially available IC's, was built and the experimental results are presented. MOS technology, which is very attractive for LSI implementation of systems with a combination of substantial amounts of digital and analog circuitries, is employed for the VLSI implementation of the new A/D converter. The circuit realization of the pipeline converter, along with the NMOS and CMOS circuit designs and SPICE simulations of all key components of the new A/D (op amps, comparators,...) are provided. These key elements are laid out and fabricated, using 4(mu) standard NMOS and 5(mu) double-poly p-well bulk CMOS technologies, and the test results are presented. The new A/D converter is digitized for VLSI fabrication, for 8- and 10-bit resolutions. The NMOS and CMOS layouts of 10-bit pipeline converters occupy only 2.3% and 4.4% of a standard chip, respectively, indicating that the pipelining technique can be employed efficiently and inexpensively for high-speed and high-accuracy applications. An analysis is carried out to investigate the second order errors caused by the imperfections of the op amps and comparators, such as finite gain and input offset voltage. A computer program is written in "C" programming language to verify the result of that analysis, as well as to perform the Monte-Carlo analysis of the new converter, for 8- and 10-bit resolutions.