9 ps gate delay Josephson OR gate with modified variable threshold logic

A Josephson logic OR gate suitable for high speed logic circuits is proposed and tested. This gate has a structure modified from Variable Threshold Logic (VTL) to obtain large operating margin and small occupation area. The operating margin is calculated as + or - 19 percent for fan-out of 2, even with the critical current variation of + or - 20 percent. The circuit area is 40 x 60 sq microns. A chain of 5-stage OR gates was fabricated. The gates had Josephson junctions of 4-microns and 7-microns diameter made with Pb-alloy technology. The minimum gate delay of 9 ps was measured using a Josephson sampler.