SEU vulnerability of the Zilog Z-80 and NSC-800 microprocessors

A detailed analysis of the SEU vulnerability of the Zilog Z-80 microprocessor is presented based upon data obtained with heavy ions and protons. The analysis demonstrates a method for separating upsets of the general purpose registers from upsets of the internal latches. Furthermore, the analysis shows that the bulk of the upsets observed below a LET value of 4 Mev-cmsq/mg is associated with upset of these internal latches. To obtain the data which made this analysis possible, a novel test technique was developed which associates all upsets with the machine cycle during which they first appear on the device pins. Limited data for the NSC-800 are included.