CMOS/SOS high soft-error threshold memory cell

The five-transistor (5T) CMOS/SOS memory cell has been widely used in radiation hardness products. The p-channel devices in the memory cell are protected from the cosmic ray hit by the buried contact diodes. However, there is no protection for the n-channel devices. A configuration referred to as seven-transistor (7T) CMOS/SOS memory cell which is modified from the 5T memory cell layout by inserting a depletion mode NMOS transistor in the feedback path of enhancement NMOS drain node has been proposed. Simulations show that this configuration increases the single event upset critical charge by a factor of 25 at Vdd-5V. The increase in silicon area is only 10 percent.