A self-testing dynamic RAM chip
Abstract
A novel approach to making very large dynamic RAM chips self-testing is presented. It is based on two main concepts: on-chip generation of regular test sequences with very high fault coverage, and concurrent testing of storage-cell arrays to reduce overall testing time. The failure modes of a typical 64 K RAM employing one-transistor cells are analyzed to identify their test requirements. A comprehensive test generation algorithm that can be implemented with minimal modification to a standard cell layout is derived. The self-checking peripheral circuits necessary to implement this testing algorithm are described, and the self-testing RAM is briefly evaluated.
- Publication:
-
IEEE Transactions on Electron Devices
- Pub Date:
- February 1985
- DOI:
- Bibcode:
- 1985ITED...32..508Y
- Keywords:
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- Chips (Memory Devices);
- Electronic Equipment Tests;
- Failure Modes;
- Random Access Memory;
- Self Tests;
- Very Large Scale Integration;
- Algorithms;
- Block Diagrams;
- Design Analysis;
- Electronics and Electrical Engineering